1. Field of the Invention
The present invention relates generally to communication devices. More particularly, the present invention relates to the testing of communication devices.
2. Background Art
Monitoring the quality of service (QoS) of a communication path has typically relied upon sporadic bit-error-rate (BER) testing. Today, communication devices go through BER testing prior to incorporation into communication networks to ensure an acceptable QoS. BER testing plays a vital role in successful development and manufacturing of communication devices. BER testing verifies compatibility with network requirements and can provide priceless diagnostic information during the critical integration testing.
BER testing is commonplace in data communication systems, and in such systems, Pseudo Random Bit Sequence (PRBS) is traditionally transmitted through the device under test (DUT) and looped back, and an error detector at the tester counts any unexpected bit as an error. Such loop-back testing is important in characterizing a DUT by a tester, screening the DUT for IEEE compliance, looking for receiver side BER on the DUT. PRBS is usually generated by applying a polynomial to a binary sequence, e.g. applying a number of XOR (exclusive OR) operations to a binary shift register, and a PRBS generator may be able to generate a PRBS with maximum pattern length of 2n−1, where n=7, 9, 11, 15, 20, 23, 31, and having N Mbits of programmable or user-defined pattern. PRBS testing is a standard and accepted method of testing due to the DC balanced and transition density of the sequence. By varying the PRBS polynomial, one can further stress the DUT.
FIG. 1 illustrates conventional testing system 100 utilizing tester device or system 110 for testing DUT 150. The approach of FIG. 1 may typically be referred to as parallel loop-back for looping back the recovered data to the transmitter through the use of FIFOs. As shown in FIG. 1, tester device 110 includes pattern generator 130, which generates a pre-defined pattern or Tx Data 132, such as a PRBS pattern. Tester device 110 also includes a transmitter or TX1 131, which transmits Tx Data 132 over a communication line, such as a wired line, wireless line or optic line, according to a local clock or C1 127, which is generated by a clock generator or (phase locked loop) PLL1 125 based on a crystal frequency or X1 120.
At the other end, the communication line is connected to DUT 150, such that DUT 150 receiver or RX2 174 receives Tx Data 132 based on a recovered C1 127 clock as Rx Data 172, and DUT 150 is configured in loop-back test mode to send Rx Data 172 to DUT 150 transmitter or TX2 171 for transmission to tester device 110, over the communication line, using the recovered C1 127 by DUT 150. Although DUT 150 includes a clock generator or (phase locked loop) PLL2 165 for generation of a local clock or C2 167 based on a crystal frequency or X2 160, C2 167 is not used by conventional testing system 100, because there is a difference in crystal frequencies X1 120 and X2 160.
Continuing with FIG. 1, tester device 110 receiver or RX1 134 receives transmitted Rx Data 172 by TX2 171, which is transmitted by DUT 150 using the recovered C1 127, shown as C1′ 173 to indicate a frequency offset between C1 127 and the recovered clock at RX2 174. Next, RX1 134 provides the received data to error detector 140, which compares the received data with Tx Data 132, provided by pattern generator 130, to detect errors and generates BER 145. However, at least one problem with the approach of conventional testing system 100 is that the recovered clock or C1′ 173 has a frequency offset with respect to C1 127, and this frequency offset causes additional non-existent bit errors due to at least the finite size of the FIFOs.
Another conventional approach is shown in FIG. 2, which illustrates conventional testing system 200 utilizing tester device 210 for testing DUT 250. The conventional approach of FIG. 2 attempts to cure the problems in the conventional approach of FIG. 1 by using a second PLL or PLL 280 at DUT 250, as explained below. As shown in FIG. 2, tester device 210 includes pattern generator 230, which generates a pre-defined pattern or Tx Data 232, such as a PRBS pattern. Tester device 210 also includes a transmitter or TX1 231, which transmits Tx Data 232 over a communication line, such as a wired line, wireless line or optic line, according to a local clock or C1 227, which is generated by PLL1 225 based on a crystal frequency or X1 220.
At the other end, the communication line is connected to DUT 250, such that DUT 250 receiver or RX2 274 receives Tx Data 232 based on a recovered C1 227 clock as Rx Data 272, and DUT 250 is configured in loop-back test mode to send Rx Data 272 to DUT 250 transmitter or TX2 271 for transmission to tester device 210, over the communication line, using C1 127 that is generated by additional PLL 280 based on the recovered clock or C1′ 273. Although DUT includes PLL2 265 for generation of a local clock or C2 267 based on a crystal frequency or X2 260, C2 267 is not used by conventional testing system 200, because there is a difference in crystal frequencies X1 220 and X2 260. However, a clock generator or (phase locked loop) PLL3 280 is added to DUT 250 for the purpose of adjusting C1′ 273 using X2 260 to generate C1 227 at DUT 250, and TX2 271 transmits RX Data 272 based on C1 227 generated at DUT 250.
Tester device 210 receiver or RX1 224 receives transmitted Rx Data 272 by TX2 271, which is transmitted by DUT 250 using C1 127 generated at DUT 250. RX1 234 provides the received data to error detector 240, which compares the received data with Tx Data 232 provided by pattern generator 230 to detect errors, and generates BER 245.
Conventional testing system 200 of FIG. 2, however, suffers from a number of drawbacks. For example, PLL3 280 increases the area of the chip in addition to increasing the power consumption, and may also cause a coupling problem with PLL 265.
Accordingly, there is a need in the art to overcome the foregoing shortcomings in the conventional approaches and introduce a reliable and efficient approach to loop-back testing in communication devices.